1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of redressing a memory cell, which in particular can redress one or more defective memory cells.
2. Background Information
With respect to a conventional semiconductor memory device, in order to rescue memory cells with deficiencies caused by variations in processes and so on, a structure which additionally adopts redundant memory cells for storing data in place of the defective memory cells has been used.
For example, Japanese Laid Open Patent Application No. 5-189996 discloses such semiconductor memory device that adopts redundant memory cells. The semiconductor memory device disclosed by Japanese Laid Open Patent Application No. 5-189996 has memory cells for normal use and redundant memory cells for use in rescue. The memory cells for normal use are disposed in one memory cell region. The redundant memory cells for use in rescue are disposed in another memory cell region. These two memory cell regions are disposed while sandwiching bonding pads between them. In this structure, when there is a defective memory cell among the memory cells in one of the memory cell regions, the semiconductor memory device uses a redundant memory cell in the other memory cell region to work in place of the defective memory cell. Therefore, when data has to be written into the address of the defective memory cell, the semiconductor memory device writes the data into the address of the redundant memory cell instead of the defective memory cell. Likewise, when data has to be read out from the address of the defective memory cell, the semiconductor memory device reads out the data from the redundant memory cell instead of the defective memory cell.
In such conventional semiconductor memory device, a redundant judging circuit for deciding whether the redundant memory cell should be used is provided. In this redundant judging circuit, the address of the defective memory cell is programmed by fuse or such in advance. The redundant judging circuit compares the input address with the programmed address (hereinafter to be referred to as the redundant address), and when the two addresses coincide, it reads out the data from the redundant memory cell or writes the data into the redundant memory cell, whichever is demanded.
However, with respect to such conventional technology, it is necessary to arrange a structure which can selectively acquire from among the data read out from the defective memory cell and the redundant memory cell only the data read out from the defective memory cell. In this respect, it is a problem that the circuit structure or the process to read out data tends to become complicated.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor memory device and an improved method of redressing a memory cell. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.